SR latch Memory

This is just some super quick update about sr latchs and a quick schematic of one I built.

A simple latch is when the output of an OR gate is one of the inputs of the OR gate.

The SR latch is more complicated but it consists of 2 OR gates.

I am just going to provide a schematic that I built but if you’d like to learn more about SR Latchs you should 100% watch this video by Ben Eater. He is awesome!

Schematic

The A1 is a button and A2 is a reset button, however you could flip them and use either.

In this configuration, the circuit maintains a ‘memory’ of which button was pressed, and it’s visialized through the LEDs.

*this was actually built more than 2 years ago and it’s been some time. I don’t exactly remember the E1 and E2 functions and I am too lazy to spend time trying to figure it out right now because I have a lot going on! Sorry!

However you could probably reverse engineer this by looking at Ben’s video and this OR Gate I built: Schematic of OR gate Good Luck! Let me know if you got it!